1. Field of the Invention
Embodiments of the present invention relate generally to dual ramp analog-to-digital converters and methods, and in specific embodiments to image sensors that include dual ramp analog-to-digital converters.
2. Related Art
Various designs for double ramp or dual ramp analog-to-digital converters (ADCs) are disclosed in U.S. Pat. No. 6,670,904, entitled “Double-Ramp ADC for CMOS Sensors”, the entire contents of which are incorporated by reference herein. U.S. Pat. No. 6,670,904 is hereinafter referred to as the '904 patent. The abstract of the '904 patent discusses a double ramp ADC that divides an analog-to-digital conversion process into two steps. During a first step of the conversion, the double ramp ADC runs through potential digital values roughly, using coarse counter steps, and maintains a coarse digital output value. During a second step of the conversion, the ADC runs through individual digital values within the range of values associated with the coarse digital value. Thus, the second step runs through fine digital values associated with the coarse digital value. The coarse and fine digital values are then output as the converted digital value of an analog input signal.
FIG. 1 illustrates a double ramp ADC 300 as disclosed in the '904 patent. As is discussed in column 3 of the '904 patent, the double ramp ADC 300 includes a capacitor 302, a switch 304, and a comparator 306. The comparator 306 receives an input voltage Vin to be converted at a first input. The input voltage Vin is an analog voltage output from a pixel within a pixel array of an image sensor or a difference between a pixel image voltage and a reset voltage output from a pixel. The capacitor 302 is connected between a fine ramp voltage Vfine and a second input of the comparator 306. The switch 304 is connected between a coarse ramp voltage Vcoarse and the second input of the comparator 306 that is connected to the capacitor 302.
FIG. 2 illustrates an example operation of the double ramp ADC 300 of FIG. 1 as disclosed in the '904 patent. As is discussed in columns 3 and 4 of the '904 patent, the example operation provides an example in which the double ramp ADC 300 has a 12-bit resolution and the output digital code, therefore, contains twelve bits, D11 through D0, with D11 being the most significant bit and D0 being the least significant bit. During the conversion process, the input voltage Vin is compared with a generated comparison voltage Vc. In the first conversion step, the fine ramp voltage Vfine is set to zero. In addition, the switch 304 is closed and the coarse ramp voltage Vcoarse is gradually changed from a maximum value to a minimum value in coarse voltage steps (i.e., steps greater than a single digital bit).
The '904 patent explains that the coarse ramp voltage Vcoarse may be associated with the most-significant bits (“MSBs”) of the output digital code, while the fine ramp voltage Vfine may be associated with the least-significant bits (“LSBs”) of the output digital code. Sometime during the first conversion step, when the coarse ramp voltage Vcoarse is less than or equal to the input voltage Vin, the comparator output voltage Vcmp changes from a one to a zero, which is a signal for control logic to latch the most significant bits in the output digital code (i.e., the bits used to generate the coarse ramp voltage Vcoarse). The control logic also uses the change in the comparator output voltage Vcmp to open the switch 304. During the time that the switch 304 was closed, the capacitor 302 was constantly being charged with the coarse ramp voltage Vcoarse. When the switch 304 is opened, the charging of the capacitor 302 is interrupted and the last coarse ramp voltage Vcoarse is saved within the capacitor 302.
The '904 patent explains that during the second conversion step, the fine ramp voltage Vfine is gradually changed from zero up to its maximum (i.e., the maximum allowable value within the range of the coarse voltage). Because the switch 304 is open, the fine ramp voltage Vfine is added to the coarse ramp voltage Vcoarse that is stored in the capacitor 302. As such, the generated comparison voltage Vc is equal to the saved coarse ramp voltage Vcoarse plus the fine ramp voltage Vfine. The generated comparison voltage Vc is compared to the input voltage Vin. Sometime during the second step, when the generated comparison voltage Vc is equal to the input voltage Vin, the comparator output voltage Vcmp changes from a zero to a one, which is a signal for the control logic to latch the least significant bits in the output digital code (i.e., the bits of the code used to generate the fine ramp voltage Vfine). The MSBs and LSBs form the converted output digital code representing the original analog input voltage Vin.
FIG. 3 illustrates an example control circuit 400 for controlling the double ramp ADC 300 of FIG. 1 as disclosed in the '904 patent. As is discussed in columns 6 and 7 of the '904 patent, the control circuit 400 includes control logic 402, a counter 404, a digital-to-analog converter (DAC) 406, and a latch circuit 408. The DAC 406 inputs a digital counter value COUNT and generates an analog ramp voltage Vramp that is sent to the double ramp ADC 300. The ramp voltage Vramp is the coarse ramp voltages Vcoarse during the first conversion step and is the fine ramp voltages Vfine during the second conversion step.
The '904 patent explains that the control logic 402 programs the counter 404 by sending it an initial counter value over the INITIAL VALUE lines, a count up/down signal over an UP/DOWN line and an increment/decrement value over the INC/DEC lines. A start/stop counter signal line START/STOP is used to start or stop the counter 404. The counter 404 inputs these signals and data and, when enabled, begins counting (up or down) with the appropriate increment/decrement every clock CLK cycle. The counter 404 outputs the digital counter value COUNT to the DAC 406 every clock CLK cycle.
As explained in the '904 patent, for the first conversion step, the control logic 402 sets the counter to the maximum count value via the INITIAL VALUE lines. The control logic 402 sets the counter to count down via the UP/DOWN line and sets the appropriate decrement value via the INC/DEC lines. To count in coarse steps, the decrement is set such that only the MSBs are decremented. When the first conversion step is to begin, the control logic 402 issues a start counter signal via the START/STOP signal line. When the control logic 402 detects that the comparator output Vcmp has switched from a one to a zero (i.e., the correct coarse voltage has been found), the control logic 402 issues a stop counter signal to the counter 404 and a latch counter signal to the latch circuit 408, which latches the counter value COUNT. The control logic 402 also changes the state of the switch 304 in the double ramp ADC 300 via the ADC SWITCH CONTROL lines to prepare for the second conversion step. The control logic 402 then resets the counter 404 for the second conversion step.
The '904 patent explains that to prepare for the second conversion step, the control logic 402 sets the counter to zero via the INITIAL VALUE lines. The control logic 402 sets the counter to count up via the UP/DOWN signal and sets the appropriate increment value via the INC/DEC lines. To count in fine steps, the increment is set to one. When the second conversion step is to begin, the control logic 402 issues a start counter signal via the START/STOP signal line. When the control logic 402 detects that the comparator output Vcmp has switched from a zero to a one (i.e., the correct coarse plus fine voltage has been found), the logic 402 issues a stop counter signal to the counter 404 and a latch counter signal to the latch circuit 408, which latches the counter value COUNT and outputs the digital code DIGITAL OUTPUT CODE corresponding to the input voltage Vin.
The '904 patent notes that the coarse ramp voltage Vcoarse could be gradually changed from a minimum value to a maximum value in coarse voltage steps if so desired, and that the fine ramp voltage Vfine could be gradually changed from a maximum value to a minimum value in fine voltage steps if so desired.
Another related art analog-to-digital converter is disclosed in J. Lee et al., “A 10b Column-wise Two-step Single-slope ADC for High-speed CMOS Image Sensor”, Int. Image Sensor Workshop, Ogunquit, Me., 2007, pp. 196-199, the entire contents of which are incorporated by reference herein.
In the related art implementations, the analog signal to be converted and the ramp are applied to different inputs of a comparator. This means that the compensation of the input signal by ramp occurs at different absolute value of the input voltage. Since the comparator must be fast, the first stage cannot have high gain. As a consequence, the comparator behaves as a non-ideal opamp with signal dependent input offset voltage. As this dependence is nonlinear in general, especially on large signals, and as the offset varies from column-to-column in an image sensor, the related art types of ADCs are likely to exhibit large column-to-column fixed pattern noise (FPN) and nonlinearity.